DS1677E【PDF 2/18 页】IC CTRLR SYSTEM PORT 20-TSSOP

DS1677

10 of 18

CU BIT TIMING Figure 5

3-WIRE SERIAL INTERFACE

Communication with the DS1677 is accomplished through a simple 3-wire interface consisting of the

Chip Select (CS), Serial Clock (SCLK) and Input/Output (I/O) pins.

All data transfers are initiated by driving the CS input high. The CS input serves two functions. First, CS

turns on the control logic, which allows access to the shift register for the address/command sequence.

Second, the CS signal provides a method of terminating either single byte or multiple byte (burst) data

transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data input, data must

be valid during the rising edge of the clock and data bits are output on the falling edge of the clock. If the

CS input goes low, all data transfer terminates and the I/O pin goes to a high impedance state.

Address and data bytes are always shifted LSB first into the I/O pin. Any transaction requires the

address/command byte to specify a read or write to a specific register followed by one or more bytes of

data. The address byte is always the first byte entered after CS is driven high. The most significant bit

( RD /WR) of this byte determines if a read or write will take place. If this bit is 0, one or more read cycles

will occur. If this bit is 1, one or more write cycles will occur.

Data transfers can occur one byte at a time or in multiple byte burst mode. After CS is driven high an

address is written to the DS1677. After the address, one or more data bytes can be read or written. For a

single byte transfer one byte is read or written and then CS is driven low. For a multiple byte transfer,

multiple bytes can be read or written to the DS1677 after the address has been written. Each read or write

cycle causes the register address to automatically increment. Incrementing continues until the device is

disabled. After accessing register 0Eh, the address wraps to 00h.

Data transfer for single byte transfer and multiple byte burst transfer is illustrated in Figures 6 and 7.

发布紧急采购，3分钟左右您将得到回复。

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购